The present application relates to semiconductor device manufacturing, and more particularly, to a method of forming a back-end-of the line (BEOL) interconnect structure having a plurality of conductive metal structures and air gaps within an interconnect dielectric material.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene interconnect structures. The interconnect structure typically includes copper, Cu, or a Cu alloy since Cu-based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al,-based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) is achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive metal structures) in an interconnect dielectric material having a dielectric constant of less than 4.0. Dielectric materials having a dielectric constant of less than 4.0 are referred to herein as low k dielectric materials.
Interconnect structures in integrated circuits induce a delay in the propagation of the information between semiconductor devices such as transistors. To reduce this delay, the interconnect structures should possess the lowest capacitance possible. One approach to form interconnect structures with the lowest possible capacitance is to introduce air (or vacuum) gaps into the interconnect dielectric material of the interconnect structure; by replacing a portion of the dielectric material with an air gap, the capacitance can be reduced dramatically.
In prior art interconnect structures, air gaps can be formed into the interconnect dielectric material by utilizing lithography and a reactive ion etch. Pattern transfer using reactive ion etching onto a conductive metal structure/interconnect dielectric material surface for the purposes of forming air gaps is however very difficult due to the formation of a polymer residue and damage induced by ion bombardment. Adjustments to the plasma parameters are limited due to the requirements for material etch selectivity and low sputter damage. Tuning of the chemistry/power setting for the plasma allows for some reduction, but not substantially all, of the damage or polymer residue generation.
As such, there is a need for providing a method of forming air gaps into an interconnect dielectric material without causing the formation of polymer residue and inducing damage into the interconnect structure. In addition, there is also a need for providing a method that can eliminate polymer residue and sputter copper material which can contaminate the plasma etch chamber.